The present invention relates to a semiconductor integrated circuit for generating an internal clock signal of a desired duty ratio from an external clock signal of any other duty ratio.
Generally, microprocessors and memory LSIs are designed to perform one-step operation in synchronism with each clock signal supplied from an external device. In other words, they perform one step of operation to receive a command, processing numerical data, input data or output data, at the rising edge or falling edge of one clock signal. Similarly, a synchronous memory, represented by a synchronous DRAM, writes data and reads data at the rising edge or falling edge of a clock signal supplied from an external device.
FIG. 1 illustrates a synchronous LSI 17. The LSI 17 receives an external clock signal EXCLK. In the LSI 17, a receiver 18 (i.e., input buffer) shapes the waveform of the signal EXCLK and amplifies the signal EXCLK, thereby generating a signal INCLK. The signal INCLK is used as an internal clock in the LSI 117.
FIG. 2A shows the waveform of an external clock signal EXCLK having a duty ratio of 50%, or a pulse duration of T/2, where T is the cycle of the signal EXCLK. Also shown in FIG. 2A is the waveform of an internal clock signal INCLK that the receiver 18 has generated from the external clock signal EXCLK. The internal clock signal INCLK is completely in phase with the external clock signal EXCLK if the delay time of the receiver 18 is neglected.
In recent years, microprocessors and synchronous memories that perform two steps of operation in synchronism with one external clock have come into use in increasing numbers, because they can operate fast. Namely, they perform one step at the rising edge of one clock signal and another step at the falling edge of the clock signal. Obviously, they operate twice faster than the microprocessors and synchronous memories designed to perform one step of operation in synchronism with one external clock signal of the same frequency. For such a microprocessor or synchronous memory it is desired that the internal clock signal have a duty ratio of 50%. The reason is as follows.
As seen from FIG. 2A, if the external clock signal EXCLK has a cycle T, the internal clock signal INCLK also has the same cycle T. Assume that a synchronous LSI (e.g., a microprocessor or a synchronous memory) needs time tp to perform one step of operation. Then, the cycle T must be at least 2 tp (T.gtoreq.2 tp) to enable the synchronous LSI to perform two steps of operation in response to one internal clock signal INCLK. If the external clock signal EXCLK has a duty ratio of 33% as illustrated in FIG. 2B, the cycle T needs to be at least 3 tp (T.gtoreq.3 tp) to enable the LSI requires to perform two steps in response to one external clock signal INCLK. This is why the internal clock signal INCLK should have a duty ratio of 50% to enable the LSI to operate at high speed.
Any external clock signal having a duty ratio other than 50% cannot enable a synchronous LSI to perform two steps of operation in response to one clock pulse at high speed.
A synchronous LSI of a special type may need an internal clock signal having a duty ratio of 25%. Hitherto, however, it has been difficult to generate an internal clock signal of a desired duty ratio, because the duty ratio of the internal clock signal totally depends upon the duty ratio of the external clock signal.